1. Field of the Invention
The present invention relates to a semiconductor memory including DRAM memory cells and including an SRAM interface.
2. Description of the Related Art
A pseudo SRAM includes DRAM memory cells (dynamic memory cells) and operates as an SRAM by internally automatically performing a refresh operation of the memory cell.
The pseudo SRAM performs the refresh operation without being recognized by a controller while a read operation and a write operation are not performed. To insert the refresh operation, for example, a read cycle time being a minimum supply interval of a read command is set to a value obtained by adding a refresh operation time to a read operation time. Further, to perform the refresh operation in priority to the read operation, a read access time from when the read command is supplied until read data is outputted includes the refresh operation time. The same goes for the write operation. As just described, in the conventional pseudo SRAM, the read cycle time and the write cycle time become longer, and thereby the data transfer rate decreases.
On the other hand, to increase the data transfer rate, a method of outputting a refresh request to the outside when the refresh request is generated inside the pseudo SRAM is proposed (for example, Japanese Unexamined Patent Application Publication No. 2005-332538). In this method, a controller which accesses the pseudo SRAM supplies an external refresh request to the pseudo SRAM in response to an internal refresh request from the pseudo SRAM. The pseudo SRAM performs the refresh operation in response to the external refresh request. The external refresh request is one of external access requests. Therefore, the refresh operation responsive to the external refresh request never contends with the read operation and the write operation. Accordingly, it becomes unnecessary to include the refresh operation time in a read operation cycle.
However, when the controller outputs the external refresh request in response to the internal refresh request from the pseudo SRAM, for example, the controller needs to interpose the external refresh request while the continuous read operation is being performed. By suspending the read operation at a timing not intended by the controller, the access efficiency drops.